1. Field of the Invention
The present invention relates to battery charging systems, and in particular, to a control system for reducing total charging time by maximizing the time high current flows across a secondary battery being charged.
2. Discussion of the Related Art
In a battery charging system for a lithium-ion or lead acid battery, a constant current (CC) mode of operation applies a high current across the discharged battery to provide rapid charging. When the battery reaches a final termination voltage, the battery charging system switches to a constant voltage (CV) mode of operation to maintain the battery at its termination voltage level. CC charging cannot be applied to the battery once it reaches its termination voltage since the energy storage capacity of the battery would be exceeded, leading to battery and charging system damage. However, in order to minimize overall charging cycle time, the CC charging time must be maximized. Therefore, the sharpness of the transition between the two modes of operation is a crucial factor in the productivity of the battery charging system. In a conventional battery charging system, the CC and CV control loops are based on a control circuit including three amplifier stages. FIG. 1 depicts a conventional battery charging circuit 100. Referring to FIG. 1, a control circuit 190 includes a CC amplifier 105 and a CV amplifier 106 that control the output of an output amplifier 108. During CC mode operation, a charging current Ibatt flowing through a battery 102 being recharged is measured by a current detector 103. CC amplifier 105 monitors the output of current detector 103 and signals output amplifier 108 to control an output voltage Vout of a power source 101 to maintain current Ibatt at a high rapid-charging current Imax. Meanwhile, CV amplifier 106 monitors the voltage across battery 102 as measured by a voltage detector 104. When the voltage across battery 102 reaches a final termination voltage Vfinal, CV amplifier 106 assumes control of output amplifier 108 and maintains voltage Vfinal across battery 102. One example of current detector 103 is shown in FIG. 3a. A current sense resistor 301 placed in series with battery 102 generates a voltage Vdc proportional to current Ibatt. In FIG. 3b, one example of voltage detector 104 includes a differential amplifier 302 that generates a voltage Vbatt which varies with the difference between voltages Vout and Vcs. Returning to FIG. 1, a voltage Vs at the non-inverting terminal and a reference voltage Vref at the inverting terminal of output amplifier 108 generate a control voltage Vc that regulates voltage Vout from power source 101. Voltage Vs is provided by summing the output currents of CC amplifier 105 and CV amplifier 106. An example of CC amplifier 105 shown in FIG. 2a includes an error amplifier 201 that compares voltage Vdc to a reference voltage Vrapid. Voltage Vrapid is defined by the following equation: EQU Vrapid=Imax*R301
where R301 is the resistance of current sense resistor 301 of FIG. 3a. At the same time, an example of CV amplifier 106 includes an error amplifier 202 to compare voltage Vbatt to final termination voltage Vfinal. Output contentions at error amplifiers 201 and 202 are prevented by diodes 203 and 204. A resistor 112 sums the current output of amplifiers 105 and 106 to provide the voltage Vs. While battery voltage Vbatt is less than voltage Vfinal, CV amplifier 106 provides a high impedance output. Therefore, error amplifier 201 is able to adjust voltage Vs as necessary to maintain voltage Vdc equal to voltage Vrapid and keep rapid-charging current Imax flowing though battery 102. However, when battery voltage Vbatt reaches voltage Vfinal, amplifier 202 rises from its low saturated state to maintain voltage Vfinal across battery 102. At the same time, current Ibatt is reduced, lowering voltage Vdc and switching CC amplifier 105 to a high impedance output. CV mode operation is then maintained by CV amplifier 106 until the fully-charged battery is replaced by a discharged battery. In this manner, battery 102 is provided with current Imax during CC mode operation and is maintained at voltage Vfinal during CV mode operation.
An alternative implementation of CC amplifier 105 and CV amplifier 106 is shown in FIG. 2b. Unidirectional transconductance error amplifiers 205 and 206 replace error amplifiers 201 and 202, respectively. Because amplifiers 205 and 206 are unidirectional, blocking diodes to prevent output contentions between the two amplifiers are not required. A pulldown resistor 112 converts the current outputs of amplifiers 205 and 206 into signal voltage Vs at summing node N1. While voltage Vbatt is less than voltage Vfinal, amplifier 206 sources no current into node N1. Therefore, the current provided by amplifier 205 controls the value of signal voltage Vs, and rapid charging current Imax flows through battery 102. Then, when voltage Vbatt reaches voltage Vfinal, the current from amplifier 206 drives voltage Vs to a level required for CV mode operation. A step-down resistor 111 at the output terminal of amplifier 205 ensures that amplifier 206 dominates the value of voltage Vs when voltage Vbatt reaches voltage Vfinal. Once again, CV mode operation is then maintained by CV amplifier 106 until fully-charged battery 102 is replaced by a discharged battery.
CC amplifier 105, CV amplifier 106, and output amplifier 108 are critical in determining the sharpness of the transition between CC and CV modes of operation. For the purpose of illustrating the effects to be discussed below, a battery can be modeled by a capacitor coupled in series with a resistor of resistance Resr ("esr" stands for "effective series resistance"). For our purpose, resistance Resr can be assumed substantially constant throughout the charging process. This battery model is illustrated in FIG. 3d.
FIG. 6, consisting of FIGS. 6a-6e, illustrates the voltage profiles of a conventional battery charging circuit and of an ideal charging circuit during a typical battery charging cycle. FIG. 6a depicts the battery low-side voltage Vdc. Vdc also represents the voltage across current detector 103 in FIG. 1 or the voltage across current sense resistor 301 in FIG. 3a when the implementation of a current detector shown is used. The battery charging current Ibatt is proportional to voltage Vdc and can be derived from the Vdc curve using the following equation: EQU Ibatt=Vdc/R103
where R103 is the resistance of current detector 103. Note that R103 equals R301 when current sense resistor 301 is used as the current detector circuit. FIG. 6b illustrates the battery voltage Vbatt. FIG. 6c illustrates the voltage Vcharge which is the resistance free voltage of the battery (i.e. the voltage across the capacitor in the battery model of FIG. 3d). In FIGS. 6a-e, charging of battery 102 commences at time T0.
Curves 602, 622, and 642, shown as dotted lines in FIGS. 6a-c, depict qualitatively the effects of a gradual transition between the CC and CV modes of operation. In comparison, curves 601, 621, and 641, shown as solid gray lines in FIGS. 6a-c, depict the ideal voltage characteristics of a battery charging circuit which minimizes the overall charging cycle time. Curve 621 (voltage Vbatt_ideal) represents the ideal battery voltage measured across the terminals of battery 102. When charging begins at time T0, Vbatt_ideal is substantially the product of the ideal charging current Ibatt_ideal and the effective series resistance Resr, assuming no residual energy is stored in battery 102 at time T0 (Ibatt_ideal is derived from voltage Vdc_ideal of curve 601 in FIG. 6a). As shown in FIG. 6b, at time T0, Vbatt_ideal is at a value of Vesr. Vbatt_ideal (curve 621) rises from this initial voltage to reach the final termination voltage Vfinal at time T1' while battery 102 is being charged under the CC mode. During the CC mode, battery 102 is being charged at a constant voltage Vdc equaling Vrapid (curve 601) and a constant charging current Ibatt equaling Imax.
At time T1', voltage Vdc ideal (curve 601) begins to decrease as CV mode takes over. Curve 601 shows that the ideal Vdc voltage decreases to a final value of Vdc/min at time T2'. In response, charging current Ibatt also decreases until a final maintenance current Imin is reached at time T2'. In FIG. 6c, curve 641 depicts voltage Vcharge_ideal which represents the charge condition of battery 102 under the conditions of ideal charging current Ibatt_ideal and ideal battery voltage Vbatt_ideal. According to the battery model, the difference between curve 621 and curve 641 results from the effective series resistance (esr) of battery 102 during the charging process. Voltage Vesr is provided by: EQU Vesr=Ibatt*Resr.
At time T1', when voltage Vbatt_ideal reaches termination voltage Vfinal, voltage Vcharge ideal (curve 641) is given by: EQU Vcharge ideal [T1']=Vfinal-Vesr(T1') =Vfinal-(Ibatt[T1']*Resr) =Vfinal-(Imax*Resr).
As CV mode takes over, charging current Ibatt decreases from current Imax and the voltage Vesr across the model resistor decreases. Consequently, voltage Vcharge_ideal (curve 641) increases, reaching the fully charged voltage Vfinal at time T2' when current Ibatt reaches Imin. AS a result, the ideal charging profile depicted by curves 601, 621 and 641 provides a minimum charging cycle time Tmin, equal to the elapsed time between times T2' and T0.
In practice, however, conventional battery charging systems are not able to deliver the optimum performance represented by curves 601, 621, and 641. The operation of amplifiers 105, 106, and 108 produces actual performance curves 602 (representing voltage Vdc_actual), 622 (representing battery voltage Vbatt_actual), and 642 (representing the "resistance-free" battery voltage Vcharge_actual), shown in dotted lines in FIGS. 6a, 6b, and 6c, respectively. In practice, as shown in curve 602, voltage Vdc_actual begins to decrease from voltage level Vrapid at time T1", prior to time T1', causing charging current Ibatt to also decrease from current level Imax at time T1" as well. As a result, the charging rate (i.e., the rate of change of Vcharge_actual, curve 642) begins to decrease from time T1" also, reaching final termination voltage at time T2". The actual charging cycle time Tactual, which is the time elapsed between times T1" and T0 is longer than Tmin, the cycle time in the ideal case. In fact, the longer battery charging cycle time is a result of the finite gains of amplifiers 105, 106, and 108. Therefore, by providing higher gains to amplifiers 105, 106 and 108, operational characteristics closer to the ideal characteristics illustrated by curves 601, 621 and 641 can be achieved.
Unfortunately, gains cannot be increased indefinitely in amplifiers used in conventional battery charging circuits due to limitations in their frequency responses. In both the CC and CV control loops of circuit 100, output amplifier 108 forms an effective two-stage amplifier with either CC amplifier 105 or CV amplifier 106. As a result, the loop response curve of each control loop includes a dominant pole at a first rolloff frequency and a secondary pole at a second rolloff frequency higher than the first rolloff frequency. Stability requirements dictate that the loop gains of the CC and CV control loops must be each less than unity when the phase shift of their respective frequency response curve reaches 180.degree.. Since each pole introduces a phase shift of 90.degree., the unity gain frequency must occur before the second rolloff frequency. One method for meeting the stability requirement is to use a single-point compensation network 107, consisting of a capacitor C303 and a resistor 304, as shown in FIG. 3c. Single-point compensation, or parallel compensation, can shift the mid-band frequency response curve of a system away from the secondary pole of the system, thereby reducing the gain at the secondary pole of the system. By properly sizing capacitor C303 and resistor R304, the unity gain frequency can be pushed below the second rolloff frequency, ensuring control loop stability.
However, while single-point compensation simplifies frequency compensation, the gain of the system is often compromised because a single-point compensation system cannot perform a pole-splitting function, which is generally necessary for properly compensating a feedback system with high loop gain. In addition, to maintain a high gain, high component values are required. Without a high gain, a quick transition from CC mode to CV mode operation cannot be achieved, thereby limiting the achievable minimum charging cycle time.
Another method to reduce the gain at the secondary pole of the system is to provide "parallel compensation." Parallel compensation is discussed in Chapter 4 of the book "Frequency Compensation Techniques for Low-power Operational Amplifiers", by R. G. H. Eschauzier, and J. H. Huijsing, published by Kluwer Academic Publishers (1995). On page 66 in that chapter, Eschauzier et al. pointed out that parallel compensation has at least two drawbacks: impractically large compensation capacitor, and difficulty in controlling multiple parameters.
Accordingly, it is desirable to provide a charging control system that enables abrupt switching between CC and CV mode operation in order to minimize battery charging cycle time.